1. Field of the Invention
The present invention relates to a device for digital frequency synthesis, and in particular to a device performing direct digital frequency synthesis.
2. Description of the Background Art
It makes it possible particularly to generate analog signals at a defined frequency, especially in a wave train, while preserving phase coherence between two bursts of the wave train at the same frequency. Two bursts of the wave train, at the same frequency, are said to be coherent if, after having artificially extended the duration of the first burst until the second burst, the phase of the second burst is the same as the phase of the first burst.
Digital synthesis is a frequency-synthesis technique which consists in calculating digitally, at regular instants, the value of the samples of the signal to be generated and in converting these samples by means of a digital/analog converter in order to generate an analog signal. Digital/analog converters are commonly designated by the abbreviation DAC according to the terminology of the art.
The frequency synthesizers obtained by this technique are very attractive as regards their volume, their weight and their energy consumption, since they can benefit from substantial integration. Their other advantages are, especially, very high resolution and very short switching times.
The French patent application No. 97 05 625, published under No. 27 63 196, filed in the name of the Applicant, has as its subject a certain type of frequency synthesizer. In such a synthesizer, the frequency synthesis is not direct since the synthesizer includes a phase loop.
The known direct digital synthesizers derive a phase law from frequency information. The phase law is derived by an accumulator. A table transforms the phase law into a sinusoidal digital signal. The sinusoidal digital signal is converted into an analog signal by a digital/analog converter. The use of a digital/analog converter introduces defects which induce the creation of parasitic spectral components. The defects are related, on the one hand, to the quantisation of the signal and, on the other hand, to the non-linearities of the DAC. In particular:
the DAC is limited to a number of bits NB which, in general, is smaller than the number of bits N with which the table calculates the sinusoidal digital signal. The change from N bits to NB bits generates a quantisation error which is conveyed by the presence of parasitic spectral lines on the signal leaving the DAC,
because of the quantisation at the input to the DAC, the transfer function of the DAC, that is to say the output voltage as a function of the digital input words, is a staircase function. The differences in height between the steps of the staircase and the existence of irregular phenomena during the transition between steps induce non-linearities. These non-linearities are added to the abovementioned quantisation error.
One known method for enhancing the spectral purity of this type of synthesizer consists in dividing the signal output by the digital/analog converter. The division is preceded by a filtering of the spectral components introduced by the sampling. This method has the major drawback of losing phase coherence because of the division operation.
One object of the invention is to remedy this drawback. By virtue of the use of a coherent accumulator and of a synchronizable divider, a device according to the invention enhances the spectral purity, by dividing the output signal from the digital synthesizer, while preserving the phase coherence, by synchronizing the divider with a synchronization signal originating from the coherent accumulator. Thus, the device preserves phase coherence between the bursts of a wave train at the same frequency, even if, between these bursts, the synthesizer has sent out a burst the frequency of which is different.
A direct digital frequency-synthesis device, according to the invention, comprises:
a modulo-M coherent accumulator, for generating a first phase law from a frequency-control word,
a table, addressed by a second phase law derived from the first phase law, for generating a digital sinusoidal signal,
a digital/analog converter for converting the digital sinusoidal signal into an analog sinusoidal signal,
a filter for filtering the analog sinusoidal signal,
and a divider, of some lower order than M, for dividing the filtered signal, the divider having a synchronization input driven by a synchronization pulse for re-synchronizing the signal after division, the synchronization pulse being derived from the phase law.
In a first embodiment, the invention consists in using the high-order bit of the phase law originating from the coherent accumulator, possessing P1 supplementary bits by comparison with the usual devices, in order to synchronize the divider. The said divider, of order 2P1, participates in the purification of the spectrum of the signal originating from the digital/analog converter.
In another embodiment, the invention consists in separating the coherent accumulator into several coherent accumulators, of lower modulo Mi than the modulo M, in such a way as to form a modulo basis in a residue-type numbering system, the outputs of the accumulators representing the phase of the signal in the basis of the modulos. A first division means, operating according to this residue-type numbering system, makes it possible to adapt the phase law; the adaptation makes it possible to go from a first representation on the basis of modulos of the accumulators to a second representation on a second modulo basis compatible with the resolution of the table, in order to be able to address the table. A second division means, operating according to this residue-type numbering system, makes it possible to adapt the phase law a second time; the adaptation makes it possible to go from the second representation to a third representation on a third modulo basis. The third modulo basis contains a single modulo equal to the division order. As in the first embodiment, a means extracts a high-order bit, of a coherent signal, in order to synchronize the divider. In this embodiment of the invention, the high-order bit is extracted from the third representation of the phase law.
The signal for synchronizing the divider is preferably a pulse; this pulse is generated by the differentiation of the falling edge of the high-order bit. The high-order bit is generally designated by the acronym MSB, the abbreviation of the terms Most Significant Bit. The pulse performs a periodic resetting of the divider. Upon a change of frequency, which corresponds to a change of burst frequency, the synchronization pulse ensures the correct placing of the phase cycle of the divider, by imposing the instant of the phase zero of the divider. Thus, the phase cycle of the divider does not depend on the history of the frequency changes as in the known devices; it depends on the phase of the high-order bit which is itself coherent, since it originates from the coherent accumulator.
Thus, when the frequency is steady, the cycle of the phase states of the divider is also steady. This is because the synchronization pulse occurs during the zero-phase state of the divider; the synchronization pulse has no effect on the progress of the phase states of the divider. Consequently, the synchronization pulse can even exhibit a temporal variation without that having any incidence on the coherence or on the spectral purity of the output signal from the divider, on condition that this temporal variation remains less than the duration of the zero-phase state of the divider.